13 Facts About Berkeley RISC

Berkeley RISC is one of two seminal research projects into reduced instruction set computer based microprocessor design taking place under the Defense Advanced Research Projects Agency Very Large Scale Integration VLSI Project.

The Berkeley RISC design was later commercialized by Sun Microsystems as the SPARC architecture, and inspired the ARM architecture.

The Berkeley RISC concept was to take advantage of both of these, producing a CPU that was the same level of complexity as the 68000, but much faster.

Since a Berkeley RISC design's ADD would actually require four instructions, the machine would have to do much more memory access to read the extra instructions, potentially slowing it down considerably.

Berkeley RISC used the concept of register windows, in which the entire "register file" was broken down into blocks, allowing the compiler to "see" one block for global variables, and another for local variables.

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Berkeley RISC I featured a two-stage instruction pipeline for additional speed, but without the complex instruction re-ordering of more modern designs.

In terms of overall performance, the Berkeley RISC I was twice as fast as the VAX, and about four times that of the Z8000.

Berkeley RISC allowed for the production of a true 32-bit processor on a real chip die using what was already an older fab.

Nevertheless, the larger register file required fewer transistors, and the final Blue design, fabbed as Berkeley RISC II, implemented all of the Berkeley RISC instruction set with only 40,760 transistors.

Berkeley RISC II proved to be much more successful in silicon and in testing outperformed almost all minicomputers on almost all tasks.

Work on the original RISC designs ended with RISC II, but the concept lived on at Berkeley.

The basic core was re-used in SOAR in 1984, basically a Berkeley RISC converted to run Smalltalk, and later in the similar VLSI-BAM that ran Prolog instead of Smalltalk.

Berkeley RISC is less famous, but more influential, for being the basis of the commercial SPARC processor design from Sun Microsystems.