14 Facts About Consistency model

In computer science, a consistency model specifies a contract between the programmer and a system, wherein the system guarantees that if the programmer follows the rules for operations on memory, memory will be consistent and the results of reading, writing, or updating memory will be predictable.

Consistency model determines whether client B will definitely see the write performed by client A, will definitely not, or cannot depend on seeing the write.

Example, a consistency model can define that a process is not allowed to issue an operation until all previously issued operations are completed.

One consistency model can be considered stronger than another if it requires all conditions of that model and more.

Under this Consistency model, a write to a variable by any processor needs to be seen instantaneously by all processors.

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Verifying sequential consistency through model checking is undecidable in general, even for finite-state cache coherence protocols.

Processor consistency model is similar to PRAM consistency model with a stronger condition that defines all writes to the same memory location must be seen in the same sequential order by all other processes.

Release consistency model relaxes the weak consistency model by distinguishing the entrance synchronization operation from the exit synchronization operation.

Such a consistency model will be useful when different matrix elements can be processed at the same time.

The processor consistency model is the most relaxed of the three models and relaxes both the constraints such that a read can complete before an earlier write even before it is made visible to other processors.

The IBM370 Consistency model has some specialised serialisation instructions which are manually placed between operations.

The Alpha Consistency model provides two types of fence instructions, memory barrier and write memory barrier.

The SPARC V9 RMO Consistency model provides a MEMBAR instruction which can be customised to order previous reads and writes with respect to future read and write operations.

The PowerPC Consistency model uses a single fence instruction called the SYNC instruction.