11 Facts About Spurious interrupt

In digital computers, an Spurious interrupt is a request for the processor to Spurious interrupt currently executing code, so that the event can be processed in a timely manner.

Consequently, all incoming hardware Spurious interrupt signals are conditioned by synchronizing them to the processor clock, and acted upon only at instruction execution boundaries.

Each Spurious interrupt signal is associated with a bit in the mask register.

On some systems, the Spurious interrupt is enabled when the bit is set, and disabled when the bit is clear.

Spurious interrupt is a hardware interrupt for which no source can be found.

The result is the processor will think another Spurious interrupt is pending, since the voltage at its Spurious interrupt request input will be not high or low enough to establish an unambiguous internal logic 1 or logic 0.

The apparent interrupt will have no identifiable source, hence the "spurious" moniker.

Software Spurious interrupt is requested by the processor itself upon executing particular instructions or when certain conditions are met.

Level-triggered Spurious interrupt is requested by holding the Spurious interrupt signal at its particular active logic level.

The important part of edge triggering is that if the Spurious interrupt was triggered by a high to low edge transition, that if the level remained low it would not trigger a further Spurious interrupt.

Shortage of Spurious interrupt lines is a problem in older system designs where the Spurious interrupt lines are distinct physical conductors.