21 Facts About Synchronous DRAM

Indeed, early SSynchronous DRAM was somewhat slower than contemporaneous burst EDO Synchronous DRAM due to the additional logic.

Today, virtually all SSynchronous DRAM is manufactured in compliance with standards established by JEDEC, an electronics industry association that adopts open standards to facilitate interoperability of electronic components.

Double data rate SSynchronous DRAM, known as DDR SSynchronous DRAM, was first demonstrated by Samsung in 1997.

SSynchronous DRAM is available in registered varieties, for systems that require greater scalability such as servers and workstations.

Today, the world's largest manufacturers of SSynchronous DRAM include: Samsung Electronics, SK Hynix, Micron Technology, and Nanya Technology.

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SSynchronous DRAM devices are internally divided into either two, four or eight independent internal data banks.

Later double-data-rate SSynchronous DRAM standards add additional mode registers, addressed using the bank address pins.

For example, DDR2 SSynchronous DRAM has a 13-bit mode register, a 13-bit extended mode register No 1, and a 5-bit extended mode register No 2 .

The SSynchronous DRAM maintains an internal counter, which iterates over all possible rows.

SSynchronous DRAM designed for battery-powered devices offers some additional power-saving options.

DDR SSynchronous DRAM employs prefetch architecture to allow quick and easy access to multiple data words located on a common physical row in the memory.

Traditional Synchronous DRAM architectures have long supported fast column access to bits on an open row.

DDR2 SSynchronous DRAM is very similar to DDR SSynchronous DRAM, but doubles the minimum read or write unit again, to four consecutive words.

The SLSynchronous DRAM Consortium consisted of about 20 major Synchronous DRAM and computer industry manufacturers.

SLSynchronous DRAM was an open standard and did not require licensing fees.

SLSynchronous DRAM used an 11-bit command bus to transmit 40-bit command packets on 4 consecutive edges of a differential command clock .

Unlike SSynchronous DRAM, there were no per-chip select signals; each chip was assigned an ID when reset, and the command contained the ID of the chip that should process it.

VCM was a proprietary type of SSynchronous DRAM that was designed by NEC, but released as an open standard with no licensing fees.

Unlike a normal SSynchronous DRAM write, which must be performed to an active row, the VCSSynchronous DRAM bank must be precharged when the restore command is issued.

Graphics double data rate SSynchronous DRAM is a type of specialized DDR SSynchronous DRAM designed to be used as the main memory of graphics processing units .

GDDR SSynchronous DRAM is distinct from commodity types of DDR SSynchronous DRAM such as DDR3, although they share some core technologies.