10 Facts About VHDL

VHDL is named after the United States Department of Defense program that created it, the Very High-Speed Integrated Circuits Program .

In 1983, VHDL was originally developed at the behest of the U S Department of Defense in order to document the behavior of the ASICs that supplier companies were including in equipment.

VHDL is generally used to write text models that describe a logic circuit.

VHDL has constructs to handle the parallelism inherent in hardware designs, but these constructs differ in syntax from the parallel constructs in Ada .

VHDL has file input and output capabilities, and can be used as a general-purpose language for text processing, but files are more commonly used by a simulation testbench for stimulus or verification data.

Related searches

Key advantage of VHDL, when used for systems design, is that it allows the behavior of the required system to be described and verified before synthesis tools translate the design into real hardware .

VHDL is a dataflow language in which every statement is considered for execution simultaneously, unlike procedural computing languages such as BASIC, C, and assembly code, where a sequence of statements is run sequentially one instruction at a time.

Big advantage of VHDL compared to original Verilog is that VHDL has a full type system.

VHDL is frequently used for two different goals: simulation of electronic designs and synthesis of such designs.

Synthesis is a process where a VHDL is compiled and mapped into an implementation technology such as an FPGA or an ASIC.