39 Facts About EDO DRAM

Unlike flash memory, EDO DRAM is volatile memory, since it loses its data quickly when power is removed.

EDO DRAM typically takes the form of an integrated circuit chip, which can consist of dozens to billions of EDO DRAM memory cells.

EDO DRAM chips are widely used in digital electronics where low-cost and high-capacity computer memory is required.

One of the largest applications for EDO DRAM is the main memory in modern computers and graphics cards (where the "main memory" is called the graphics memory).

In contrast, SRAM, which is faster and more expensive than EDO DRAM, is typically used where speed is of greater concern than cost and size, such as the cache memories in processors.

Related searches

EDO DRAM filed a patent in 1967, and was granted U S patent number 3, 387, 286 in 1968.

MOS EDO DRAM chips were commercialized in 1969 by Advanced Memory system, Inc of Sunnyvale, CA.

The first commercial SEDO DRAM chip was the Samsung KM48SL2000, which had a capacity of 16Mb, and was introduced in 1992.

EDO DRAM is usually arranged in a rectangular array of charge storage cells consisting of one capacitor and transistor per data bit.

Some EDO DRAM matrices are many thousands of cells in height and width.

Under some conditions, most of the data in EDO DRAM can be recovered even if the EDO DRAM has not been refreshed for several minutes.

Each bit of data in a EDO DRAM is stored as a positive or negative electrical charge in a capacitive structure.

Up until the mid-1980s, the capacitors in EDO DRAM cells were co-planar with the access transistor, thus they were referred to as planar capacitors.

EDO DRAM cells featuring capacitors above the substrate are referred to as stacked or folded plate capacitors.

One-transistor, zero-capacitor EDO DRAM cell has been a topic of research since the late-1990s.

Refreshing of cells remains necessary, but unlike with 1T1C EDO DRAM, reads in 1T EDO DRAM are non-destructive; the stored charge causes a detectable shift in the threshold voltage of the transistor.

EDO DRAM cells are laid out in a regular rectangular, grid-like pattern to facilitate their control and access via wordlines and bitlines.

EDO DRAM cell area is given as n F, where n is a number derived from the EDO DRAM cell design, and F is the smallest feature size of a given process technology.

Bitline length is limited by the amount of operating current the EDO DRAM can draw and by how power can be dissipated, since these two characteristics are largely determined by the charging and discharging of the bitline.

Besides ensuring that the lengths of the bitlines and the number of attached EDO DRAM cells attached to them are equal, two basic architectures to array design have emerged to provide for the requirements of the sense amplifiers: open and folded bitline arrays.

Under some conditions most of the data in EDO DRAM can be recovered even if it has not been refreshed for several minutes.

An asynchronous EDO DRAM chip has power connections, some number of address inputs, and a few (typically one or four) bidirectional data lines.

Page mode EDO DRAM is a minor modification to the first-generation EDO DRAM IC interface which improved the performance of reads and writes to a row by avoiding the inefficiency of precharging and opening the same row repeatedly to access a different column.

Page mode EDO DRAM was later improved with a small modification which further reduced latency.

In page mode EDO DRAM, was asserted before the column address was supplied.

Related searches

Fast page mode EDO DRAM was introduced in 1986 and was used with Intel 80486.

Single-cycle EDO DRAM has the ability to carry out a complete memory transaction in one clock cycle.

Additionally, for systems with an L2 cache, the availability of EDO DRAM memory improved the average memory latency seen by applications over earlier FPM implementations.

Single-cycle EDO DRAM became very popular on video cards towards the end of the 1990s.

BEDO DRAM added a pipeline stage allowing page-access cycle to be divided into two parts.

Single data rate SEDO DRAM is the original generation of SEDO DRAM; it made a single transfer of data per clock cycle.

Double data rate SEDO DRAM was a later development of SEDO DRAM, used in PC memory beginning in 2000.

Video EDO DRAM is a dual-ported variant of EDO DRAM that was once commonly used to store the frame-buffer in some graphics adaptors.

Window EDO DRAM is a variant of VRAM that was once used in graphics adaptors such as the Matrox Millennium and ATI 3D Rage Pro.

Multibank EDO DRAM is a type of specialized EDO DRAM developed by MoSys.

MEDO DRAM allows operations to two banks in a single clock cycle, permitting multiple concurrent accesses to occur if the accesses were independent.

MEDO DRAM was primarily used in graphic cards, such as those featuring the Tseng Labs ET6x00 chipsets.

Graphics double data rate SEDO DRAM is a type of specialized DDR SEDO DRAM designed to be used as the main memory of graphics processing units.

GDDR SEDO DRAM is distinct from commodity types of DDR SEDO DRAM such as DDR3, although they share some core technologies.