The early MIPS II architectures were 32-bit; 64-bit versions were developed later.
| FactSnippet No. 1,665,650 |
25 Facts About MIPS II
1.
2.
In March 2021, MIPS II announced that the development of the MIPS II architecture had ended as the company is making the transition to RISC-V.
| FactSnippet No. 1,665,651 |
3.
When MIPS II was introduced, MIPS was renamed MIPS I to distinguish it from the new version.
| FactSnippet No. 1,665,652 |
4.
MIPS II V was completed by the integer-only MDMX extension to provide a complete system for improving the performance of 3D graphics applications.
| FactSnippet No. 1,665,653 |
5.
When MIPS II Technologies was spun-out of Silicon Graphics in 1998, it refocused on the embedded market.
| FactSnippet No. 1,665,654 |
7.
MIPS II is a modular architecture supporting up to four coprocessors.
| FactSnippet No. 1,665,656 |
8.
MIPS II I has instructions that load and store 8-bit bytes, 16-bit halfwords, and 32-bit words.
| FactSnippet No. 1,665,657 |
9.
Since MIPS II I is a 32-bit architecture, loading quantities fewer than 32 bits requires the datum to be either sign-extended or zero-extended to 32 bits.
| FactSnippet No. 1,665,658 |
10.
MIPS II I requires all memory accesses to be aligned to their natural word boundaries, otherwise an exception is signaled.
| FactSnippet No. 1,665,659 |
11.
MIPS II I has instructions to perform bitwise logical AND, OR, XOR, and NOR.
| FactSnippet No. 1,665,660 |
12.
MIPS II I has instructions to perform left and right logical shifts and right arithmetic shifts.
| FactSnippet No. 1,665,661 |
13.
MIPS II I has instructions for signed and unsigned integer multiplication and division.
| FactSnippet No. 1,665,662 |
14.
MIPS II I has two instructions for software to signal an exception: System Call and Breakpoint.
| FactSnippet No. 1,665,663 |
15.
MIPS II removed the load delay slot and added several sets of instructions.
| FactSnippet No. 1,665,664 |
16.
MIPS II IV was designed to mainly improve floating-point performance.
| FactSnippet No. 1,665,665 |
17.
MIPS II IV added several new FP arithmetic instructions for both single- and double-precision FPNs: fused-multiply add or subtract, reciprocal, and reciprocal square-root.
| FactSnippet No. 1,665,666 |
18.
MIPS II V added a new data type, the Paired Single, which consisted of two single-precision floating-point numbers stored in the existing 64-bit floating-point registers.
| FactSnippet No. 1,665,667 |
19.
MIPS II has had several calling conventions, especially on the 32-bit platform.
| FactSnippet No. 1,665,668 |
20.
MIPS II EABI is supported by GCC but not LLVM, and neither supports NUBI.
| FactSnippet No. 1,665,669 |
21.
MIPS II processors are used in embedded systems such as residential gateways and routers.
| FactSnippet No. 1,665,670 |
22.
MIPS II processors used to be popular in supercomputers during the 1990s, but all such systems have dropped off the TOP500 list.
| FactSnippet No. 1,665,671 |
23.
Sample MIPS II-based platforms include both bare metal environments and platforms for booting unmodified Linux binary images.
| FactSnippet No. 1,665,672 |
24.
MARS is another GUI-based MIPS II emulator designed for use in education, specifically for use with Hennessy's Computer Organization and Design.
| FactSnippet No. 1,665,673 |
25.
WebMIPS II is a browser-based MIPS II simulator with visual representation of a generic, pipelined processor.
| FactSnippet No. 1,665,674 |