RISC-V is an open standard instruction set architecture based on established RISC principles.
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RISC-V is an open standard instruction set architecture based on established RISC principles.
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Unlike most other ISA designs, RISC-V is provided under open source licenses that do not require fees to use.
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Notable features of the RISC-V ISA include instruction bit field locations chosen to simplify the use of multiplexers in a CPU, a design that is architecturally neutral, and most-significant bits of immediate values placed at a fixed location to speed sign extension.
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RISC-V was begun with a goal to make a practical ISA that was open-sourced, usable academically, and deployable in any hardware or software design without royalties.
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The RISC-V authors are academics who have substantial experience in computer design, and the RISC-V ISA is a direct development from a series of academic computer-design projects, especially Berkeley RISC.
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David Patterson at Berkeley joined the collaboration as he was the originator of the Berkeley RISC, and the RISC-V is the eponymous fifth generation of his long series of cooperative RISC-based research projects.
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In November 2019, the RISC-V Foundation announced that it would relocate to Switzerland, citing concerns over US trade regulations.
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RISC-V has a modular design, consisting of alternative base parts, with added optional extensions.
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RISC-V has 32 integer registers, and, when the floating-point extension is implemented, separate 32 floating-point registers.
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RISC-V was originally specified as little-endian to resemble other familiar, successful computers, for example, x86.
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The RISC-V instruction set decodes starting at the lowest-addressed byte of the instruction.
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RISC-V manages memory systems that are shared between CPUs or threads by ensuring a thread of execution always sees its memory operations in the programmed order.
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RISC-V uses a SPARC-like combination of 12-bit offsets and 20-bit set upper instructions.
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RISC-V's subroutine call jal places its return address in a register.
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RISC-V has no save multiple or restore multiple register instructions.
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RISC-V defines nine possible operations: swap ; add; bitwise and, or, and exclusive-or; and signed and unsigned minimum and maximum.
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Some unpopular parts of this proposal were that it added a condition code, the first in a RISC-V design, linked adjacent registers, and has a loop counter that can be difficult to implement in some microarchitectures.
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So, the RISC-V proposal is more like a Cray's long-vector design or ARM's Scalable Vector Extension.
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RISC-V organization maintains a list of RISC-V CPU and SoC implementations.
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RISC-V software includes toolchains, operating systems, middleware and design software.
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