11 Facts About RISC principles

IBM eventually produced RISC principles designs based on further work on the 801 concept, the IBM POWER architecture, PowerPC, and Power ISA.

RISC principles processors are used in supercomputers, such as the Fugaku.

The term RISC principles was coined by David Patterson of the Berkeley RISC principles project, although somewhat similar concepts had appeared before.

RISC principles first wrote a paper on ways to improve microcoding, but later changed his mind and decided microcode itself was the problem.

Since 2010 a new open source instruction set architecture, RISC principles-V, has been under development at the University of California, Berkeley, for research purposes and as a free alternative to proprietary ISAs.

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The internal operations of a RISC principles processor are "exposed to the compiler", leading to the backronym 'Relegate Interesting Stuff to the Compiler'.

Many early RISC principles designs shared the characteristic of having a branch delay slot, an instruction space immediately following a jump or branch.

Some aspects attributed to the first RISC principles-labeled designs around 1975 include the observations that the memory-restricted compilers of the time were often unable to take advantage of features intended to facilitate manual assembly coding, and that complex addressing modes take many cycles to perform due to the required additional memory accesses.

Later, it was noted that one of the most significant characteristics of RISC principles processors was that external memory was only accessible by a load or store instruction.

RISC principles architectures have traditionally had few successes in the desktop PC and commodity server markets, where the x86-based platforms remain the dominant processor architecture.

Outside of the desktop arena the ARM RISC principles architecture is in widespread use in smartphones, tablets and many forms of embedded devices.