22 Facts About PCI bus

Devices connected to the PCI bus appear to a bus master to be connected directly to its own bus and are assigned addresses in the processor's address space.

Typical PCI cards used in PCs include: network cards, sound cards, modems, extra ports such as Universal Serial Bus or serial, TV tuner cards and hard disk drive host adapters.

The first PCI bus specification was developed by Intel, but subsequent development of the standard became the responsibility of the PCI bus Special Interest Group .

In mainstream PCs, PCI bus was slower to replace VLB, and did not gain significant market penetration until late 1994 in second-generation Pentium PCs.

Outside the server market, the 64-bit version of plain PCI bus remained rare in practice though, although it was used for example by all G3 and G4 Power Macintosh computers.

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The PCI bus includes four interrupt pins, later allow up to 8 PCI devices share the same interrupt line in APIC systems, all of which are available to each device.

Later revisions of the PCI bus specification add support for message-signaled interrupts.

PCI bus Express does not have physical interrupt lines at all.

Typical PCI bus cards have either one or two key notches, depending on their signaling voltage.

PCI bus connector is defined as having 62 contacts on each side of the edge connector, but two or four of them are replaced by key notches, so a card has 60 or 58 contacts on each side.

The standard size for Mini PCI bus cards is approximately a quarter of their full-sized counterparts.

Many Mini PCI bus devices were developed such as Wi-Fi, Fast Ethernet, Bluetooth, modems, sound cards, cryptographic accelerators, SCSI, IDE–ATA, SATA controllers and combination cards.

Mini PCI bus has been superseded by the much narrower PCI bus Express Mini Card.

Each PCI bus slot gets its own configuration space address range.

Target abandons a delayed transaction when a retry succeeds in delivering the buffered result, the PCI bus is reset, or when 2=32768 clock cycles elapse without seeing a retry.

Generally, when a PCI bus bridge sees a transaction on one PCI bus that must be forwarded to the other, the original transaction must wait until the forwarded transaction completes before a result is ready.

PCI bus transactions are controlled by five main control signals, two driven by the initiator of a transaction, and three driven by the target .

All PCI bus signals are sampled on the rising edge of the clock.

PCI bus requires that every time the device driving a PCI bus signal changes, one turnaround cycle must elapse between the time the one device stops driving the signal and the other device starts.

The PCI bus protocol is designed so this is rarely a limitation; only in a few special cases is it necessary to insert additional delay to meet this requirement.

PCI bus detects parity errors, but does not attempt to correct them by retrying operations; it is purely a failure indication.

Logic analyzers and PCI bus analyzers are tools which collect, analyze, and decode signals for users to view in useful ways.