12 Facts About POWER1

POWER1 is a multi-chip CPU developed and fabricated by IBM that implemented the POWER instruction set architecture.

An indirect derivative of the POWER1 is the PowerPC 601, a feature-reduced variant of the RSC intended for consumer applications.

POWER1 is notable as it represented a number of firsts for IBM and computing in general.

For computing firsts, the POWER1 would be known for being the first CPU to implement some form of register renaming and out-of-order execution, a technique that improves the performance of superscalar processors but was previously reserved for mainframes.

POWER1 was the origin for the highly successful families of POWER, PowerPC and Power ISA processors that followed it, measuring in hundreds of different implementations.

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POWER1 is a big-endian CPU that uses a Harvard style cache hierarchy with separate instruction and data caches.

IBM used clustering to overcome this disadvantage in POWER1 systems, allowing them to effectively function as if they were multiprocessing systems, a concept proven by the popularity of SP1 supercomputers based on the POWER1.

POWER1 is a multi-chip CPU built from separate chips that are connected to each other by buses.

The total number of transistors featured by the POWER1, assuming that it is a RIOS-1 configuration, is 6.

For execution, the FXU contains the POWER1's fixed-point register file, an arithmetic logic unit for general instructions, and a dedicated fixed-point multiply and divide unit.

POWER1's floating point unit executes floating-point instructions issue by the ICU.

POWER1 has a 64 KB data cache implemented through four identical data-cache units, each containing 16 KB of data cache.