44 Facts About Dynamic RAM

Unlike flash memory, DDynamic RAM is volatile memory, since it loses its data quickly when power is removed.

DDynamic RAM typically takes the form of an integrated circuit chip, which can consist of dozens to billions of DDynamic RAM memory cells.

DDynamic RAM chips are widely used in digital electronics where low-cost and high-capacity computer memory is required.

One of the largest applications for DDynamic RAM is the main memory in modern computers and graphics cards .

In contrast, SDynamic RAM, which is faster and more expensive than DDynamic RAM, is typically used where speed is of greater concern than cost and size, such as the cache memories in processors.

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MOS DDynamic RAM chips were commercialized in 1969 by Advanced Memory system, Inc of Sunnyvale, CA.

The first commercial SDDynamic RAM chip was the Samsung KM48SL2000, which had a capacity of 16Mb, and was introduced in 1992.

DDynamic RAM is usually arranged in a rectangular array of charge storage cells consisting of one capacitor and transistor per data bit.

Some DDynamic RAM matrices are many thousands of cells in height and width.

Under some conditions, most of the data in DDynamic RAM can be recovered even if the DDynamic RAM has not been refreshed for several minutes.

When such a Dynamic RAM is accessed by clocked logic, the times are generally rounded up to the nearest clock cycle.

Each bit of data in a DDynamic RAM is stored as a positive or negative electrical charge in a capacitive structure.

Up until the mid-1980s, the capacitors in DDynamic RAM cells were co-planar with the access transistor, thus they were referred to as planar capacitors.

DDynamic RAM cells featuring capacitors above the substrate are referred to as stacked or folded plate capacitors.

One-transistor, zero-capacitor DDynamic RAM cell has been a topic of research since the late-1990s.

Refreshing of cells remains necessary, but unlike with 1T1C DDynamic RAM, reads in 1T DDynamic RAM are non-destructive; the stored charge causes a detectable shift in the threshold voltage of the transistor.

DDynamic RAM cells are laid out in a regular rectangular, grid-like pattern to facilitate their control and access via wordlines and bitlines.

DDynamic RAM cell area is given as n F, where n is a number derived from the DDynamic RAM cell design, and F is the smallest feature size of a given process technology.

Bitline length is limited by the amount of operating current the DDynamic RAM can draw and by how power can be dissipated, since these two characteristics are largely determined by the charging and discharging of the bitline.

Besides ensuring that the lengths of the bitlines and the number of attached DDynamic RAM cells attached to them are equal, two basic architectures to array design have emerged to provide for the requirements of the sense amplifiers: open and folded bitline arrays.

Under some conditions most of the data in DDynamic RAM can be recovered even if it has not been refreshed for several minutes.

Dynamic RAM ICs are usually packaged in molded epoxy cases, with an internal lead frame for interconnections between the silicon die and the package leads.

DDynamic RAM that is integrated into an integrated circuit designed in a logic-optimized process is called embedded DDynamic RAM .

An asynchronous DDynamic RAM chip has power connections, some number of address inputs, and a few bidirectional data lines.

Page mode DDynamic RAM is a minor modification to the first-generation DDynamic RAM IC interface which improved the performance of reads and writes to a row by avoiding the inefficiency of precharging and opening the same row repeatedly to access a different column.

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Page mode DDynamic RAM was later improved with a small modification which further reduced latency.

In page mode DDynamic RAM, was asserted before the column address was supplied.

Fast page mode DDynamic RAM was introduced in 1986 and was used with Intel 80486.

Single-cycle EDO DDynamic RAM became very popular on video cards towards the end of the 1990s.

Synchronous dynamic RAM significantly revises the asynchronous memory interface, adding a clock line.

Single data rate SDDynamic RAM is the original generation of SDDynamic RAM; it made a single transfer of data per clock cycle.

Double data rate SDDynamic RAM was a later development of SDDynamic RAM, used in PC memory beginning in 2000.

Video DDynamic RAM is a dual-ported variant of DDynamic RAM that was once commonly used to store the frame-buffer in some graphics adaptors.

Window DDynamic RAM is a variant of VDynamic RAM that was once used in graphics adaptors such as the Matrox Millennium and ATI 3D Rage Pro.

WDynamic RAM was designed to perform better and cost less than VDynamic RAM.

Multibank DDynamic RAM is a type of specialized DDynamic RAM developed by MoSys.

MDDynamic RAM allows operations to two banks in a single clock cycle, permitting multiple concurrent accesses to occur if the accesses were independent.

MDDynamic RAM was primarily used in graphic cards, such as those featuring the Tseng Labs ET6x00 chipsets.

Synchronous graphics Dynamic RAM is a specialized form of SDDynamic RAM for graphics adaptors.

Graphics double data rate SDDynamic RAM is a type of specialized DDR SDDynamic RAM designed to be used as the main memory of graphics processing units .

GDDR SDDynamic RAM is distinct from commodity types of DDR SDDynamic RAM such as DDR3, although they share some core technologies.

Pseudostatic RAM is dynamic RAM with built-in refresh and address-control circuitry to make it behave similarly to static RAM .

PSDynamic RAM is used in the Apple iPhone and other embedded systems such as XFlar Platform.

Cypress Semiconductor's HyperDynamic RAM is a type of PSDynamic RAM supporting a JEDEC-compliant 8-pin HyperBus or Octal xSPI interface.