29 Facts About Instruction cache

CPU cache is a hardware cache used by the central processing unit of a computer to reduce the average cost to access data from the main memory.

The Instruction cache memory is typically implemented with static random-access memory, in modern CPUs by far the largest part of them by chip area, but SRAM is not always used for all levels, or even any level, sometimes some latter or all levels are implemented with eDRAM.

The first CPUs that used a cache had only one level of cache; unlike later level 1 cache, it was not split into L1d and L1i.

Split L1 Instruction cache started in 1976 with the IBM 801 CPU, became mainstream in the late 1980s, and in 1997 entered the embedded CPU market with the ARMv5TE.

The L2 Instruction cache is usually not split and acts as a common repository for the already split L1 Instruction cache.

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L4 Instruction cache is currently uncommon, and is generally on dynamic random-access memory, rather than on static random-access memory, on a separate die or chip.

Alternatively, in a write-back or copy-back Instruction cache, writes are not immediately mirrored to the main memory, and the Instruction cache instead tracks which locations have been written over, marking them as dirty.

The Instruction cache hit rate and the Instruction cache miss rate play an important role in determining this performance.

One benefit of this scheme is that the tags stored in the Instruction cache do not have to include that part of the main memory address which is implied by the Instruction cache memory's index.

Since the Instruction cache tags have fewer bits, they require fewer transistors, take less space on the processor circuit board or on the microprocessor chip, and can be read and compared faster.

An effective memory address which goes along with the Instruction cache line is split into the tag, the index and the block offset.

An instruction cache requires only one flag bit per cache row entry: a valid bit.

The first hardware cache used in a computer system was not actually a data or instruction cache, but rather a TLB.

Alternatively, if Instruction cache entries are allowed on pages not mapped by the TLB, then those entries will have to be flushed when the access rights on those pages are changed in the page table.

Also, during miss processing, the alternate ways of the Instruction cache line indexed have to be probed for virtual aliases and any matches evicted.

Since virtual hints have fewer bits than virtual tags distinguishing them from one another, a virtually hinted Instruction cache suffers more conflict misses than a virtually tagged Instruction cache.

Cache entry replacement policy is determined by a Instruction cache algorithm selected to be implemented by the processor designers.

The victim Instruction cache is usually fully associative, and is intended to reduce the number of conflict misses.

Micro-operation cache is a specialized cache that stores micro-operations of decoded instructions, as received directly from the instruction decoders or from the instruction cache.

Branch target cache or branch target instruction cache, the name used on ARM microprocessors, is a specialized cache which holds the first few instructions at the destination of a taken branch.

Smart Instruction cache is a level 2 or level 3 caching method for multiple execution cores, developed by Intel.

Furthermore, the shared Instruction cache makes it faster to share memory among different execution cores.

Typically, sharing the L1 Instruction cache is undesirable because the resulting increase in latency would make each core run considerably slower than a single-core chip.

An associative Instruction cache is more complicated, because some form of tag must be read to determine which entry of the Instruction cache to select.

An N-way set-associative level-1 Instruction cache usually reads all N possible tags and N data in parallel, and then chooses the data associated with the matching tag.

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Early history of Instruction cache technology is closely tied to the invention and use of virtual memory.

The popularity of on-motherboard Instruction cache continued through the Pentium MMX era but was made obsolete by the introduction of SDRAM and the growing disparity between bus clock rates and CPU clock rates, which caused on-motherboard Instruction cache to be only slightly faster than main memory.

Early Instruction cache designs focused entirely on the direct cost of Instruction cache and RAM and average execution speed.

Multi-ported Instruction cache is a Instruction cache which can serve more than one request at a time.