47 Facts About EDO RAM

Unlike flash memory, DEDO RAM is volatile memory, since it loses its data quickly when power is removed.

DEDO RAM typically takes the form of an integrated circuit chip, which can consist of dozens to billions of DEDO RAM memory cells.

DEDO RAM chips are widely used in digital electronics where low-cost and high-capacity computer memory is required.

One of the largest applications for DEDO RAM is the main memory in modern computers and graphics cards .

In contrast, SEDO RAM, which is faster and more expensive than DEDO RAM, is typically used where speed is of greater concern than cost and size, such as the cache memories in processors.

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MOS DEDO RAM chips were commercialized in 1969 by Advanced Memory system, Inc of Sunnyvale, CA.

The first commercial SDEDO RAM chip was the Samsung KM48SL2000, which had a capacity of 16Mb, and was introduced in 1992.

DEDO RAM is usually arranged in a rectangular array of charge storage cells consisting of one capacitor and transistor per data bit.

Some DEDO RAM matrices are many thousands of cells in height and width.

Under some conditions, most of the data in DEDO RAM can be recovered even if the DEDO RAM has not been refreshed for several minutes.

When such a EDO RAM is accessed by clocked logic, the times are generally rounded up to the nearest clock cycle.

Each bit of data in a DEDO RAM is stored as a positive or negative electrical charge in a capacitive structure.

Up until the mid-1980s, the capacitors in DEDO RAM cells were co-planar with the access transistor, thus they were referred to as planar capacitors.

DEDO RAM cells featuring capacitors above the substrate are referred to as stacked or folded plate capacitors.

One-transistor, zero-capacitor DEDO RAM cell has been a topic of research since the late-1990s.

Refreshing of cells remains necessary, but unlike with 1T1C DEDO RAM, reads in 1T DEDO RAM are non-destructive; the stored charge causes a detectable shift in the threshold voltage of the transistor.

DEDO RAM cells are laid out in a regular rectangular, grid-like pattern to facilitate their control and access via wordlines and bitlines.

DEDO RAM cell area is given as n F, where n is a number derived from the DEDO RAM cell design, and F is the smallest feature size of a given process technology.

Bitline length is limited by the amount of operating current the DEDO RAM can draw and by how power can be dissipated, since these two characteristics are largely determined by the charging and discharging of the bitline.

Besides ensuring that the lengths of the bitlines and the number of attached DEDO RAM cells attached to them are equal, two basic architectures to array design have emerged to provide for the requirements of the sense amplifiers: open and folded bitline arrays.

Under some conditions most of the data in DEDO RAM can be recovered even if it has not been refreshed for several minutes.

Dynamic EDO RAM ICs are usually packaged in molded epoxy cases, with an internal lead frame for interconnections between the silicon die and the package leads.

DEDO RAM that is integrated into an integrated circuit designed in a logic-optimized process is called embedded DEDO RAM .

An asynchronous DEDO RAM chip has power connections, some number of address inputs, and a few bidirectional data lines.

Page mode DEDO RAM is a minor modification to the first-generation DEDO RAM IC interface which improved the performance of reads and writes to a row by avoiding the inefficiency of precharging and opening the same row repeatedly to access a different column.

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Page mode DEDO RAM was later improved with a small modification which further reduced latency.

In page mode DEDO RAM, was asserted before the column address was supplied.

Fast page mode DEDO RAM was introduced in 1986 and was used with Intel 80486.

EDO RAM, sometimes referred to as Hyper Page Mode enabled DRAM, is similar to Fast Page Mode DRAM with the additional feature that a new access cycle can be started while keeping the data output of the previous cycle active.

Single-cycle EDO RAM has the ability to carry out a complete memory transaction in one clock cycle.

Additionally, for systems with an L2 cache, the availability of EDO RAM memory improved the average memory latency seen by applications over earlier FPM implementations.

Single-cycle EDO DRAM became very popular on video cards towards the end of the 1990s.

BEDO RAM added a pipeline stage allowing page-access cycle to be divided into two parts.

Synchronous dynamic EDO RAM significantly revises the asynchronous memory interface, adding a clock line.

Single data rate SDEDO RAM is the original generation of SDEDO RAM; it made a single transfer of data per clock cycle.

Double data rate SDEDO RAM was a later development of SDEDO RAM, used in PC memory beginning in 2000.

Video DEDO RAM is a dual-ported variant of DEDO RAM that was once commonly used to store the frame-buffer in some graphics adaptors.

Window DEDO RAM is a variant of VEDO RAM that was once used in graphics adaptors such as the Matrox Millennium and ATI 3D Rage Pro.

WEDO RAM was designed to perform better and cost less than VEDO RAM.

Multibank DEDO RAM is a type of specialized DEDO RAM developed by MoSys.

MDEDO RAM allows operations to two banks in a single clock cycle, permitting multiple concurrent accesses to occur if the accesses were independent.

MDEDO RAM was primarily used in graphic cards, such as those featuring the Tseng Labs ET6x00 chipsets.

Synchronous graphics EDO RAM is a specialized form of SDEDO RAM for graphics adaptors.

Graphics double data rate SDEDO RAM is a type of specialized DDR SDEDO RAM designed to be used as the main memory of graphics processing units .

GDDR SDEDO RAM is distinct from commodity types of DDR SDEDO RAM such as DDR3, although they share some core technologies.

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PSEDO RAM is used in the Apple iPhone and other embedded systems such as XFlar Platform.

Cypress Semiconductor's HyperEDO RAM is a type of PSEDO RAM supporting a JEDEC-compliant 8-pin HyperBus or Octal xSPI interface.